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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-14 02:29:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-14 03:05:55 +0100 |
| commit | 6132e6e72a95a6f57e209bfa801c4ac5c1faa974 (patch) | |
| tree | 4692638b2e2b7009464c16ecef38ca01bb03a8ef | |
| parent | 590e6961cb2ff352c2c01d5fcf6307db95d37129 (diff) | |
| download | yosys-6132e6e72a95a6f57e209bfa801c4ac5c1faa974.tar.gz yosys-6132e6e72a95a6f57e209bfa801c4ac5c1faa974.tar.bz2 yosys-6132e6e72a95a6f57e209bfa801c4ac5c1faa974.zip | |
Fix a bug in clk2fflogic memory handling
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index d334cf7d9..7e952e99b 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -126,7 +126,7 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); - SigSpec en_q = module->addWire(NEW_ID, GetSize(addr)); + SigSpec en_q = module->addWire(NEW_ID, GetSize(en)); module->addFf(NEW_ID, en, en_q); SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr)); |