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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-10-24 12:13:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-24 12:13:09 +0200 |
| commit | 61440a42d1b8b2c5dfa50d1fd2aec4766664f6b2 (patch) | |
| tree | 58074b48e48a63310776776d00a0953e7fa7a1c7 | |
| parent | c0e4d01aa7ee1ae349a4d7637336a50831b79a6d (diff) | |
| parent | 49945ab1c29482344a36c17eefde44243de90972 (diff) | |
| download | yosys-61440a42d1b8b2c5dfa50d1fd2aec4766664f6b2.tar.gz yosys-61440a42d1b8b2c5dfa50d1fd2aec4766664f6b2.tar.bz2 yosys-61440a42d1b8b2c5dfa50d1fd2aec4766664f6b2.zip | |
Merge pull request #3523 from lparkes/basename
Replace GNU specific invocation of basename(1) with the equivalent POSIX one
| -rwxr-xr-x | tests/sim/run-test.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sim/run-test.sh b/tests/sim/run-test.sh index d34d1f3c9..a5120e77e 100755 --- a/tests/sim/run-test.sh +++ b/tests/sim/run-test.sh @@ -3,7 +3,7 @@ set -eu source ../gen-tests-makefile.sh echo "Generate FST for sim models" find tb/* -name tb*.v | while read name; do - test_name=$(basename -s .v $name) + test_name=$(basename $name .v) echo "Test $test_name" verilog_name=${test_name:3}.v iverilog -o tb/$test_name.out $name $verilog_name |