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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-26 19:11:55 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-26 23:56:54 +0200 |
| commit | 62311b7ec0fc92fd78c38dd416551d460f1647a2 (patch) | |
| tree | 0a3be7860e46a0f17c69b22aed8e2acde3f476d6 | |
| parent | 9bcde4d82b92c02f0659714d48f3ea01aec3d1cd (diff) | |
| download | yosys-62311b7ec0fc92fd78c38dd416551d460f1647a2.tar.gz yosys-62311b7ec0fc92fd78c38dd416551d460f1647a2.tar.bz2 yosys-62311b7ec0fc92fd78c38dd416551d460f1647a2.zip | |
intel_alm: increase abc9 -W
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 2 | ||||
| -rw-r--r-- | tests/arch/intel_alm/mux.ys | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index b751e8413..9c3ae1743 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -258,7 +258,7 @@ struct SynthIntelALMPass : public ScriptPass { if (check_label("map_luts")) { run("techmap -map +/intel_alm/common/abc9_map.v"); - run(stringf("abc9 %s -maxlut 6 -W 200", help_mode ? "[-dff]" : dff ? "-dff" : "")); + run(stringf("abc9 %s -maxlut 6 -W 600", help_mode ? "[-dff]" : dff ? "-dff" : "")); run("techmap -map +/intel_alm/common/abc9_unmap.v"); run("techmap -map +/intel_alm/common/alm_map.v"); run("opt -fast"); diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index 8277e925f..01cc78e1b 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -47,9 +47,9 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:MISTRAL_ALUT5 -select -assert-count 1 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-count 1 t:MISTRAL_ALUT3 +select -assert-count 2 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D design -load read @@ -69,9 +69,9 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 2 t:MISTRAL_ALUT5 -select -assert-count 4 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-count 1 t:MISTRAL_ALUT3 +select -assert-count 5 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D design -load read |