diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:53:48 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:53:48 -0800 |
| commit | 64ace4b0dc5c8dd24132bc8046b2bacc163f9164 (patch) | |
| tree | cd7058058b92e17e8c21fa2254e21cc1ba5f1a03 | |
| parent | d152fe961ffb3d7ed0493cde5c21f88fe78644e1 (diff) | |
| download | yosys-64ace4b0dc5c8dd24132bc8046b2bacc163f9164.tar.gz yosys-64ace4b0dc5c8dd24132bc8046b2bacc163f9164.tar.bz2 yosys-64ace4b0dc5c8dd24132bc8046b2bacc163f9164.zip | |
Fixes
| -rw-r--r-- | passes/techmap/abc9.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3c781ca44..f82511407 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -411,6 +411,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip if (mapped_mod == NULL) log_error("ABC output file does not contain a module `$__abc9__'.\n"); + for (auto w : mapped_mod->wires()) + module->addWire(remap_name(w->name), GetSize(w)); + dict<IdString, bool> abc9_box; vector<RTLIL::Cell*> boxes; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { |