Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

29 files changed, 196 insertions, 121 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3599e19e3..445103771 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -599,25 +599,46 @@ struct XAigerWriter
 			RTLIL::Module *holes_module = module->design->addModule("$__holes__");
 			log_assert(holes_module);
 
+			dict<IdString, Cell*> cell_cache;
+
 			int port_id = 1;
 			int box_count = 0;
 			for (auto cell : box_list) {
-				RTLIL::Module* box_module = module->design->module(cell->type);
+				RTLIL::Module* orig_box_module = module->design->module(cell->type);
+				log_assert(orig_box_module);
+				IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
+				RTLIL::Module* box_module = module->design->module(derived_name);
+				if (box_module->has_processes())
+					log_error("ABC9 box '%s' contains processes!\n", box_module->name.c_str());
+
 				int box_inputs = 0, box_outputs = 0;
-				Cell *holes_cell = nullptr;
-				if (box_module->get_bool_attribute("\\whitebox")) {
+				auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
+				Cell *holes_cell = r.first->second;
+				if (r.second && box_module->get_bool_attribute("\\whitebox")) {
 					holes_cell = holes_module->addCell(cell->name, cell->type);
 					holes_cell->parameters = cell->parameters;
+					r.first->second = holes_cell;
+
+					// Since Module::derive() will create a new module, there
+					//   is a chance that the ports will be alphabetically ordered
+					//   again, which is a problem when carry-chains are involved.
+					//   Inherit the port ordering from the original module here...
+					//   (and set the port_id below, when iterating through those)
+					log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
+					box_module->ports = orig_box_module->ports;
 				}
 
 				// NB: Assume box_module->ports are sorted alphabetically
 				//     (as RTLIL::Module::fixup_ports() would do)
+				int box_port_id = 1;
 				for (const auto &port_name : box_module->ports) {
 					RTLIL::Wire *w = box_module->wire(port_name);
 					log_assert(w);
+					if (r.second)
+						w->port_id = box_port_id++;
 					RTLIL::Wire *holes_wire;
-					RTLIL::SigSpec port_wire;
-					if (w->port_input) {
+					RTLIL::SigSpec port_sig;
+					if (w->port_input)
 						for (int i = 0; i < GetSize(w); i++) {
 							box_inputs++;
 							holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
@@ -628,28 +649,29 @@ struct XAigerWriter
 								holes_module->ports.push_back(holes_wire->name);
 							}
 							if (holes_cell)
-								port_wire.append(holes_wire);
+								port_sig.append(holes_wire);
 						}
-						if (!port_wire.empty())
-							holes_cell->setPort(w->name, port_wire);
-					}
 					if (w->port_output) {
 						box_outputs += GetSize(w);
 						for (int i = 0; i < GetSize(w); i++) {
 							if (GetSize(w) == 1)
-								holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
+								holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), log_id(w->name)));
 							else
-								holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
+								holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
 							holes_wire->port_output = true;
 							holes_wire->port_id = port_id++;
 							holes_module->ports.push_back(holes_wire->name);
 							if (holes_cell)
-								port_wire.append(holes_wire);
+								port_sig.append(holes_wire);
 							else
 								holes_module->connect(holes_wire, State::S0);
 						}
-						if (!port_wire.empty())
-							holes_cell->setPort(w->name, port_wire);
+					}
+					if (!port_sig.empty()) {
+						if (r.second)
+							holes_cell->setPort(w->name, port_sig);
+						else
+							holes_module->connect(holes_cell->getPort(w->name), port_sig);
 					}
 				}
 
@@ -679,14 +701,11 @@ struct XAigerWriter
 				RTLIL::Selection& sel = holes_module->design->selection_stack.back();
 				sel.select(holes_module);
 
-				// TODO: Should not need to opt_merge if we only instantiate
-				//       each box type once...
-				Pass::call(holes_module->design, "opt_merge -share_all");
-
 				Pass::call(holes_module->design, "flatten -wb");
 
-				// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
-				//       instead of per write_xaiger call
+				// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
+				//   since boxes may contain parameters in which case `flatten` would have
+				//   created a new $paramod ...
 				Pass::call(holes_module->design, "techmap");
 				Pass::call(holes_module->design, "aigmap");
 				for (auto cell : holes_module->cells())
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index b29480e26..279b32223 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1767,7 +1767,7 @@ struct AbcPass : public Pass {
 		extra_args(args, argidx, design);
 
 		if (!lut_costs.empty() && !liberty_file.empty())
-			log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
+			log_cmd_error("Got -lut and -liberty! These two options are exclusive.\n");
 		if (!constr_file.empty() && liberty_file.empty())
 			log_cmd_error("Got -constr but no -liberty!\n");
 
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f467218cc..0d3ec4e5b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,5 +1,6 @@
 // ---------------------------------------
 
+(* lib_whitebox *)
 module LUT4(input A, B, C, D, output Z);
     parameter [15:0] INIT = 16'h0000;
     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
@@ -31,13 +32,8 @@ module CCU2C(
 
 	// First half
 	wire LUT4_0, LUT2_0;
-`ifdef _ABC
-	assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
-	assign LUT2_0 = INIT0[{2'b00, B0, A0}];
-`else
 	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
 	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
-`endif
 	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
 	assign S0 = LUT4_0 ^ gated_cin_0;
 
@@ -46,13 +42,8 @@ module CCU2C(
 
 	// Second half
 	wire LUT4_1, LUT2_1;
-`ifdef _ABC
-	assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
-	assign LUT2_1 = INIT1[{2'b00, B1, A1}];
-`else
 	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
 	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
-`endif
 	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 	assign S1 = LUT4_1 ^ gated_cin_1;
 
@@ -209,6 +200,7 @@ endmodule
 
 // ---------------------------------------
 
+(* lib_whitebox *)
 module LUT2(input A, B, output Z);
     parameter [3:0] INIT = 4'h0;
     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b71bb2395..a0ea6d1f9 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3bcbfc9aa..72e684af5 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1112,8 +1112,8 @@ module RAM16X1D_1 (
 endmodule
 
 module RAM32X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc9_arrival=1153 *)
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+  (* abc9_arrival=1188 *)
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
@@ -1135,8 +1135,8 @@ module RAM32X1D (
 endmodule
 
 module RAM32X1D_1 (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc9_arrival=1153 *)
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+  (* abc9_arrival=1188 *)
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
@@ -1158,7 +1158,7 @@ module RAM32X1D_1 (
 endmodule
 
 module RAM64X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
   (* abc9_arrival=1153 *)
   output DPO, SPO,
   input  D,
@@ -1181,7 +1181,7 @@ module RAM64X1D (
 endmodule
 
 module RAM64X1D_1 (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
   (* abc9_arrival=1153 *)
   output DPO, SPO,
   input  D,
@@ -1204,8 +1204,9 @@ module RAM64X1D_1 (
 endmodule
 
 module RAM128X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc9_arrival=1153 *)
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+  //   plus 204ps to cross MUXF7
+  (* abc9_arrival=1357 *)
   output DPO, SPO,
   input        D,
   (* clkbuf_sink *)
@@ -1244,9 +1245,18 @@ endmodule
 // Multi port.
 
 module RAM32M (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc9_arrival=1153 *)
-  output [1:0] DOA, DOB, DOC, DOD,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+  (* abc9_arrival=1188 *)
+  output [1:0] DOA,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+  (* abc9_arrival=1187 *)
+  output [1:0] DOB,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+  (* abc9_arrival=1180 *)
+  output [1:0] DOC,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+  (* abc9_arrival=1190 *)
+  output [1:0] DOD,
   input [4:0] ADDRA, ADDRB, ADDRC, ADDRD,
   input [1:0] DIA, DIB, DIC, DID,
   (* clkbuf_sink *)
@@ -1347,9 +1357,18 @@ module RAM32M16 (
 endmodule
 
 module RAM64M (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
   (* abc9_arrival=1153 *)
-  output DOA, DOB, DOC, DOD,
+  output DOA,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc9_arrival=1161 *)
+  output DOB,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+  (* abc9_arrival=1158 *)
+  output DOC,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+  (* abc9_arrival=1163 *)
+  output DOD,
   input [5:0] ADDRA, ADDRB, ADDRC, ADDRD,
   input DIA, DIB, DIC, DID,
   (* clkbuf_sink *)
@@ -1508,7 +1527,7 @@ module SRL16 (
 endmodule
 
 module SRL16E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
   (* abc9_arrival=1472 *)
   output Q,
   input A0, A1, A2, A3, CE,
@@ -1572,9 +1591,10 @@ module SRLC16E (
 endmodule
 
 module SRLC32E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
   (* abc9_arrival=1472 *)
   output Q,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
   (* abc9_arrival=1114 *)
   output Q31,
   input [4:0] A,
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a19046911..d4095e449 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
 		log("    -ise\n");
-		log("        generate an output netlist suitable for ISE (enables -iopad)\n");
+		log("        generate an output netlist suitable for ISE\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        do not use block RAM cells in output netlist\n");
@@ -84,11 +84,9 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nodsp\n");
 		log("        do not use DSP48E1s to implement multipliers and associated logic\n");
 		log("\n");
-		log("    -iopad\n");
-		log("        enable I/O buffer insertion (selected automatically by -ise)\n");
-		log("\n");
 		log("    -noiopad\n");
-		log("        disable I/O buffer insertion (only useful with -ise)\n");
+		log("        disable I/O buffer insertion (useful for hierarchical or \n");
+		log("        out-of-context flows)\n");
 		log("\n");
 		log("    -noclkbuf\n");
 		log("        disable automatic clock buffer insertion\n");
@@ -122,7 +120,7 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, family;
-	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
+	bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
 	bool flatten_before_abc;
 	int widemux;
 
@@ -136,7 +134,6 @@ struct SynthXilinxPass : public ScriptPass
 		retime = false;
 		vpr = false;
 		ise = false;
-		iopad = false;
 		noiopad = false;
 		noclkbuf = false;
 		nocarry = false;
@@ -213,7 +210,6 @@ struct SynthXilinxPass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-iopad") {
-				iopad = true;
 				continue;
 			}
 			if (args[argidx] == "-noiopad") {
@@ -282,7 +278,6 @@ struct SynthXilinxPass : public ScriptPass
 
 	void script() YS_OVERRIDE
 	{
-		bool do_iopad = iopad || (ise && !noiopad);
 		std::string ff_map_file;
 		if (help_mode)
 			ff_map_file = "+/xilinx/{family}_ff_map.v";
@@ -517,8 +512,8 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			// Needs to be done before logic optimization, so that inverters (OE vs T) are handled.
-			if (help_mode || do_iopad)
-				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
+			if (help_mode || !noiopad)
+				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if not '-noiopad')");
 			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys
new file mode 100644
index 000000000..1d1682fcd
--- /dev/null
+++ b/tests/arch/ecp5/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+        input clk,
+        output ledc
+    );
+ 
+    reg [6:0] led_counter = 0;
+    always @( posedge clk ) begin
+            led_counter <= led_counter + 1;
+    end
+    assign ledc = !led_counter[ 6:3 ];
+ 
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 92463aa32..22866832d 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -39,8 +39,8 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 8 t:L6MUX21
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:PFUMX
+select -assert-count 12 t:L6MUX21
+select -assert-count 34 t:LUT4
+select -assert-count 17 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys
new file mode 100644
index 000000000..8438cb979
--- /dev/null
+++ b/tests/arch/ice40/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+        input clk,
+        output ledc
+    );
+ 
+    reg [6:0] led_counter = 0;
+    always @( posedge clk ) begin
+            led_counter <= led_counter + 1;
+    end
+    assign ledc = !led_counter[ 6:3 ];
+ 
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index 9dbddce47..313948cc5 100644
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 14 t:LUT2
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index c0ff6a2e2..3328f9edc 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -40,7 +40,7 @@ select -assert-none t:BUFG t:FDSE %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys
index 4c881b280..7bdd94a63 100644
--- a/tests/arch/xilinx/attributes_test.ys
+++ b/tests/arch/xilinx/attributes_test.ys
@@ -1,7 +1,7 @@
 # Check that blockram memory without parameters is not modified
 read_verilog ../common/memory_attributes/attributes_test.v
 hierarchy -top block_ram
-synth_xilinx -top block_ram
+synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAMB18E1
  
@@ -9,7 +9,7 @@ select -assert-count 1 t:RAMB18E1
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
 hierarchy -top distributed_ram
-synth_xilinx -top distributed_ram
+synth_xilinx -top distributed_ram -noiopad
 cd distributed_ram # Constrain all select calls below inside the top module
 select -assert-count 8 t:RAM32X1D
  
@@ -18,7 +18,7 @@ design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
 prep
 setattr -mod -set ram_style "distributed" block_ram
-synth_xilinx -top block_ram
+synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 32 t:RAM128X1D
  
@@ -27,7 +27,7 @@ design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
 prep
 setattr -mod -set logic_block 1 block_ram
-synth_xilinx -top block_ram
+synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 0 t:RAMB18E1
 select -assert-count 32 t:RAM128X1D
@@ -35,13 +35,13 @@ select -assert-count 32 t:RAM128X1D
 # Set ram_style block to a distributed memory; will be implemented as blockram
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
-synth_xilinx -top distributed_ram_manual
+synth_xilinx -top distributed_ram_manual -noiopad
 cd distributed_ram_manual # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAMB18E1
  
 # Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
-synth_xilinx -top distributed_ram_manual_syn
+synth_xilinx -top distributed_ram_manual_syn -noiopad
 cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAMB18E1
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index bb908cbbf..ed743cf44 100644
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -3,28 +3,28 @@
 # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
 design -reset
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
 design -reset
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
 design -reset
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
@@ -32,7 +32,7 @@ select -assert-count 1 t:RAMB18E1
 design -reset
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 0 t:RAMB18E1
 select -assert-count 4 t:RAM128X1D
@@ -41,7 +41,7 @@ select -assert-count 4 t:RAM128X1D
 design -reset
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB36E1
 
@@ -52,7 +52,7 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
 setattr -set ram_style "block" m:memory
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
@@ -60,7 +60,7 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
 setattr -set ram_block 1 m:memory
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
@@ -68,7 +68,7 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
 setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 0 t:RAMB18E1
 
@@ -76,7 +76,7 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
 setattr -set logic_block 1 m:memory
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 0 t:RAMB18E1
 
@@ -84,7 +84,7 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
 
@@ -92,6 +92,6 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
 setattr -set ram_block 1 m:memory
-synth_xilinx -top sync_ram_sdp
+synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys
index 2018071cc..09935ccd8 100644
--- a/tests/arch/xilinx/bug1460.ys
+++ b/tests/arch/xilinx/bug1460.ys
@@ -28,7 +28,7 @@ module register_file(
 endmodule
 EOT
 
-synth_xilinx
+synth_xilinx -noiopad
 cd register_file
 select -assert-count 32 t:RAM32M
 select -assert-none t:* t:BUFG %d t:RAM32M %d
diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys
new file mode 100644
index 000000000..1175380b1
--- /dev/null
+++ b/tests/arch/xilinx/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+        input clk,
+        output ledc
+    );
+ 
+    reg [6:0] led_counter = 0;
+    always @( posedge clk ) begin
+            led_counter <= led_counter + 1;
+    end
+    assign ledc = !led_counter[ 6:3 ];
+ 
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 604acdbfc..11c29922e 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
index 0bba4858f..dc764b033 100644
--- a/tests/arch/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDRE %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys
index f9185551b..ca6b619b9 100644
--- a/tests/arch/xilinx/dsp_cascade.ys
+++ b/tests/arch/xilinx/dsp_cascade.ys
@@ -19,7 +19,7 @@ EOT
 proc
 design -save read
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48E1
@@ -35,7 +35,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D
 select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
 
 design -load read
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48A1
@@ -65,7 +65,7 @@ EOT
 proc
 design -save read
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 design -load postopt
 cd cascade
 select -assert-count 2 t:DSP48E1
@@ -75,7 +75,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D
 select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
 
 design -load read
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 2 t:DSP48A1
diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys
index 0067a822b..57fe49bde 100644
--- a/tests/arch/xilinx/dsp_fastfir.ys
+++ b/tests/arch/xilinx/dsp_fastfir.ys
@@ -63,7 +63,7 @@ module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_re
 endmodule
 EOT
 
-synth_xilinx
+synth_xilinx -noiopad
 cd fastfir_dynamictaps
 select -assert-count 2 t:DSP48E1
 select -assert-none t:* t:DSP48E1 %d t:BUFG %d
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index f03400fe7..3235d5af3 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
 
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index c87a8e38b..e226c2ec8 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top latchp
 proc
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D
 design -load read
 hierarchy -top latchn
 proc
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -26,7 +26,7 @@ select -assert-none t:LDCE t:INV %% t:* %D
 design -load read
 hierarchy -top latchsr
 proc
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index d5b5c1a37..61a9314cc 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys
index 6c9d1eae1..3f127a77e 100644
--- a/tests/arch/xilinx/lutram.ys
+++ b/tests/arch/xilinx/lutram.ys
@@ -2,7 +2,7 @@
 #hierarchy -top lutram_1w1r -chparam A_WIDTH 4
 #proc
 #memory -nomap
-#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 #memory
 #opt -full
 #
@@ -22,7 +22,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 5
 proc
 memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 memory
 opt -full
 
@@ -42,7 +42,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 memory
 opt -full
 
@@ -62,7 +62,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w3r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 memory
 opt -full
 
@@ -82,7 +82,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w3r -chparam A_WIDTH 6
 proc
 memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 memory
 opt -full
 
@@ -102,7 +102,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
 proc
 memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 memory
 opt -full
 
@@ -122,7 +122,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
 proc
 memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 memory
 opt -full
 
diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys
index 11e959976..bf2b36320 100644
--- a/tests/arch/xilinx/macc.ys
+++ b/tests/arch/xilinx/macc.ys
@@ -3,8 +3,8 @@ design -save read
 
 hierarchy -top macc
 proc
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
@@ -17,8 +17,8 @@ select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
 design -load read
 hierarchy -top macc2
 proc
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
index 6cf994fbf..490846ff1 100644
--- a/tests/arch/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/mul.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -13,7 +13,7 @@ design -reset
 read_verilog ../common/mul.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys
index c714680af..980263cbd 100644
--- a/tests/arch/xilinx/mul_unsigned.ys
+++ b/tests/arch/xilinx/mul_unsigned.ys
@@ -2,7 +2,7 @@ read_verilog mul_unsigned.v
 hierarchy -top mul_unsigned
 proc
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -16,7 +16,7 @@ read_verilog mul_unsigned.v
 hierarchy -top mul_unsigned
 proc
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 388272449..99817738d 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
@@ -14,7 +14,7 @@ select -assert-none t:LUT3 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT6
@@ -25,7 +25,7 @@ select -assert-none t:LUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
@@ -37,7 +37,7 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-min 5 t:LUT6
diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys
index 455437f18..3652319a0 100644
--- a/tests/arch/xilinx/shifter.ys
+++ b/tests/arch/xilinx/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys
index 4697703ca..eaccab126 100644
--- a/tests/arch/xilinx/tribuf.ys
+++ b/tests/arch/xilinx/tribuf.ys
@@ -7,6 +7,7 @@ synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
-# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D
+select -assert-count 2 t:IBUF
+select -assert-count 1 t:INV
+select -assert-count 1 t:OBUFT
+select -assert-none t:IBUF t:INV t:OBUFT %% t:* %D