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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-11 13:46:01 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:28:04 -0700 |
| commit | 66aac06eeef177318f3a4ade150e20a21be7e7c7 (patch) | |
| tree | 6526ed451422495bd9b81a5f9ca6e254462541c8 | |
| parent | cca3cb5fbbe5ba127b620be5435697fb0ee66736 (diff) | |
| download | yosys-66aac06eeef177318f3a4ade150e20a21be7e7c7.tar.gz yosys-66aac06eeef177318f3a4ade150e20a21be7e7c7.tar.bz2 yosys-66aac06eeef177318f3a4ade150e20a21be7e7c7.zip | |
Removed commented out debug code
| -rw-r--r-- | passes/opt/opt_rmports.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/passes/opt/opt_rmports.cc b/passes/opt/opt_rmports.cc index 2fd73fff2..6c80e2b7c 100644 --- a/passes/opt/opt_rmports.cc +++ b/passes/opt/opt_rmports.cc @@ -42,10 +42,6 @@ struct OptRmportsPass : public Pass { virtual void execute(std::vector<std::string> /*args*/, RTLIL::Design *design) { log_header(design, "Executing OPT_RMPORTS pass (remove top level ports with no connections).\n"); - - //vector<RTLIL::Module*> mods = design->modules(); - //for(auto mod : mods) - // ProcessModule(mod); ProcessModule(design->top_module()); } |