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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 13:13:10 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-23 13:13:10 -0700 |
| commit | 67a4850e3505e97bcb01fb02a688beee89af6e76 (patch) | |
| tree | abca4263ba6df2c3d7d749ee4d566fb56c374263 | |
| parent | ca4694735455512162da1d4a24429ecf350a8abe (diff) | |
| parent | 99a3fee8f4a0f89f865ccf5292d5e70d59febd9f (diff) | |
| download | yosys-67a4850e3505e97bcb01fb02a688beee89af6e76.tar.gz yosys-67a4850e3505e97bcb01fb02a688beee89af6e76.tar.bz2 yosys-67a4850e3505e97bcb01fb02a688beee89af6e76.zip | |
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
Add "min bits" and "min wports" to xilinx dram rules
| -rw-r--r-- | techlibs/xilinx/drams.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt index e6635d0e2..91632bcee 100644 --- a/techlibs/xilinx/drams.txt +++ b/techlibs/xilinx/drams.txt @@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D endbram match $__XILINX_RAM64X1D + min bits 5 + min wports 1 make_outreg or_next_if_better endmatch match $__XILINX_RAM128X1D + min bits 9 + min wports 1 make_outreg endmatch |