diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:04:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 13:39:37 -0800 |
| commit | 67be62a957c565bfa03f084c8f110d65ca14196b (patch) | |
| tree | 263033883286b4c8e3babfff5165c6bfe01790c3 | |
| parent | 15aa3f460d1aa873108360df1cf2d5f22137946d (diff) | |
| download | yosys-67be62a957c565bfa03f084c8f110d65ca14196b.tar.gz yosys-67be62a957c565bfa03f084c8f110d65ca14196b.tar.bz2 yosys-67be62a957c565bfa03f084c8f110d65ca14196b.zip | |
clkpart to analyse async flops too
| -rw-r--r-- | passes/hierarchy/clkpart.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc index b79625540..15a5328b9 100644 --- a/passes/hierarchy/clkpart.cc +++ b/passes/hierarchy/clkpart.cc @@ -162,6 +162,14 @@ struct ClkPartPass : public Pass { key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec()); } else + if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), + ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_))) + { + bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)); + log_assert(!enable_mode); // TODO + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); + } + else continue; unassigned_cells.erase(cell); |