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| author | Patrick Urban <patrick.urban@web.de> | 2021-09-24 21:52:09 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-13 21:53:25 +0100 |
| commit | 6825de6343e2b104ccad3d9ae6bf657deb80014e (patch) | |
| tree | cee40f06cd449ff790d992a9abbb33f8082ac732 | |
| parent | acb993b27b7027112bf10796efbf2886815f8630 (diff) | |
| download | yosys-6825de6343e2b104ccad3d9ae6bf657deb80014e.tar.gz yosys-6825de6343e2b104ccad3d9ae6bf657deb80014e.tar.bz2 yosys-6825de6343e2b104ccad3d9ae6bf657deb80014e.zip | |
synth_gatemate: Registers are uninitialized
| -rw-r--r-- | techlibs/gatemate/cells_sim.v | 4 | ||||
| -rw-r--r-- | techlibs/gatemate/synth_gatemate.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 0c9287b81..c1cacc6d1 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -294,7 +294,7 @@ module CC_DFF #( assign en = (EN_INV) ? ~EN : EN;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'b0;
+ initial Q = 1'bX;
always @(posedge clk or posedge sr)
begin
@@ -323,7 +323,7 @@ module CC_DLT #( assign en = (G_INV) ? ~G : G;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'b0;
+ initial Q = 1'bX;
always @(*)
begin
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index 27a2b5bfa..b570e1e2a 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -305,7 +305,7 @@ struct SynthGateMatePass : public ScriptPass if (check_label("map_regs"))
{
run("opt_clean");
- run("dfflegalize -cell $_DFFE_????_ 0 -cell $_DLATCH_???_ 0");
+ run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
|