diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-26 17:52:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-26 17:52:57 -0700 |
| commit | 6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16 (patch) | |
| tree | 8cc15936e0efcf99a0d02b1feaa7d298cbefb8a4 | |
| parent | 54422c5bb4cdd3488fa1849af9049d0f4bb24603 (diff) | |
| download | yosys-6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16.tar.gz yosys-6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16.tar.bz2 yosys-6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16.zip | |
Revert "In sat: 'x' in init attr should not override constant"
This reverts commit 2b37a093e95036b267481b2dae2046278eef4040.
| -rw-r--r-- | passes/sat/sat.cc | 2 | ||||
| -rw-r--r-- | tests/sat/initval.v | 4 | ||||
| -rw-r--r-- | tests/sat/initval.ys | 2 |
3 files changed, 1 insertions, 7 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index bcc690fa3..dd56d8c71 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,8 +268,6 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (bit.is_fully_const() && rhs[i] == State::Sx) - rhs[i] = bit; if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..5b661f8d6 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,7 +1,6 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; - reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -12,8 +11,5 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; - always @* - asdf[2:0] <= 3'b111; - assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts |