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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 15:32:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 15:32:58 -0700 |
| commit | 6b9ca7cd6d14ac5e3ebf8354849a5c31d9a3a49b (patch) | |
| tree | d44fe2bfa6c9a72ce75c2f19ecbd8b8f9d9e813f | |
| parent | dcc8a13e481c058f17b98ea900f9feb9192ea5ae (diff) | |
| download | yosys-6b9ca7cd6d14ac5e3ebf8354849a5c31d9a3a49b.tar.gz yosys-6b9ca7cd6d14ac5e3ebf8354849a5c31d9a3a49b.tar.bz2 yosys-6b9ca7cd6d14ac5e3ebf8354849a5c31d9a3a49b.zip | |
Remove split_shiftx call
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b6b22284c..1320673e5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -126,7 +126,6 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n"); - log(" split_shiftx (without '-nosrl' and '-nomux' only)\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); @@ -310,10 +309,8 @@ struct SynthXilinxPass : public Pass // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former // Also: wide multiplexer inference benefits from this too - if (!nosrl || !nomux) { + if (!nosrl || !nomux) Pass::call(design, "pmux2shiftx"); - Pass::call(design, "split_shiftx"); - } if (!nosrl) { // shregmap operates on bit-level flops, not word-level, |