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authorClifford Wolf <clifford@clifford.at>2019-05-01 10:01:54 +0200
committerClifford Wolf <clifford@clifford.at>2019-05-01 10:01:54 +0200
commit6bbe2fdbf32e6335cdbecc21547e54992c3a606d (patch)
tree7ce91013e7b348d059f6c87e3aad62f6b1b0fbd6
parent3b6a02d3a74dc0113d595c6d26a4436160e28a6f (diff)
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Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
-rw-r--r--frontends/ast/simplify.cc1
-rw-r--r--tests/simple/mem2reg.v22
2 files changed, 23 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 4d4b9dfe1..d6561682a 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1607,6 +1607,7 @@ skip_dynamic_range_lvalue_expansion:;
current_scope[wire_tmp->str] = wire_tmp;
wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { }
+ wire_tmp->is_logic = true;
AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER);
wire_tmp_id->str = wire_tmp->str;
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 9839fd4a8..100426785 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
assign out = bar[foo[0]];
endmodule
+// ------------------------------------------------------
+
+module mem2reg_test6 (din, dout);
+ input wire [3:0] din;
+ output reg [3:0] dout;
+
+ reg [1:0] din_array [1:0];
+ reg [1:0] dout_array [1:0];
+
+ always @* begin
+ din_array[0] = din[0 +: 2];
+ din_array[1] = din[2 +: 2];
+
+ dout_array[0] = din_array[0];
+ dout_array[1] = din_array[1];
+
+ {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
+
+ dout[0 +: 2] = dout_array[0];
+ dout[2 +: 2] = dout_array[1];
+ end
+endmodule