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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-26 16:21:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-26 16:21:30 -0700 |
| commit | 6ca7844ceca934064e8914c9dd0853eaaa495bad (patch) | |
| tree | 7623e16e91fcc7e40a8ecea9dde9d435fab75cba | |
| parent | f97b90e40b9a9b8e8b8ea692c651464980721ce4 (diff) | |
| download | yosys-6ca7844ceca934064e8914c9dd0853eaaa495bad.tar.gz yosys-6ca7844ceca934064e8914c9dd0853eaaa495bad.tar.bz2 yosys-6ca7844ceca934064e8914c9dd0853eaaa495bad.zip | |
kernel: const Wire* overload -> Wire* !!!
| -rw-r--r-- | kernel/sigtools.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 10b39a89e..c631fa481 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -300,7 +300,7 @@ struct SigMap add(bit); } - inline void add(const Wire *wire) { return add(RTLIL::SigSpec(wire)); } + inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); } void apply(RTLIL::SigBit &bit) const { |