Merge pull request #1325 from YosysHQ/eddie/sat_init

In sat: 'x' in init attr should be ignored

2 files changed, 8 insertions, 2 deletions

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index dd56d8c71..430bba1e8 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -268,7 +268,7 @@ struct SatHelper
 				RTLIL::SigSpec removed_bits;
 				for (int i = 0; i < lhs.size(); i++) {
 					RTLIL::SigSpec bit = lhs.extract(i, 1);
-					if (!satgen.initial_state.check_all(bit)) {
+					if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
 						removed_bits.append(bit);
 						lhs.remove(i, 1);
 						rhs.remove(i, 1);
diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index 5b661f8d6..81f71b5ba 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,6 +1,7 @@
-module test(input clk, input [3:0] bar, output [3:0] foo);
+module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
+  reg [3:0] asdf = 4'b1xxx;
 
   always @*
     foo[1:0] <= bar[1:0];
@@ -11,5 +12,10 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
+  always @(posedge clk)
+    asdf[3] <= bar[3];
+  always @*
+    asdf[2:0] = 3'b111;
+
   assert property (foo == {last_bar[3:2], bar[1:0]});
 endmodule