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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-03 10:00:18 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-03 10:00:18 +0200 |
| commit | 721fa1cbd87c52a3adfce260f35fc33a7ae7ac4d (patch) | |
| tree | 942c9891ff50ee5f5596261b6777a09e540d86f7 | |
| parent | 3f6554d698b8857c47e7cc9b452517dd7cbbee6b (diff) | |
| parent | 6acbc016f43b1464e6322b895f16d01ed51eea18 (diff) | |
| download | yosys-721fa1cbd87c52a3adfce260f35fc33a7ae7ac4d.tar.gz yosys-721fa1cbd87c52a3adfce260f35fc33a7ae7ac4d.tar.bz2 yosys-721fa1cbd87c52a3adfce260f35fc33a7ae7ac4d.zip | |
Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
| -rw-r--r-- | passes/memory/memory_bram.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 85ed1c053..804aa21f9 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -957,6 +957,8 @@ grow_read_ports:; SigSpec addr_ok_q = addr_ok; if ((pi.clocks || pi.make_outreg) && !addr_ok.empty()) { addr_ok_q = module->addWire(NEW_ID); + if (!pi.sig_en.empty()) + addr_ok = module->Mux(NEW_ID, addr_ok_q, addr_ok, pi.sig_en); module->addDff(NEW_ID, pi.sig_clock, addr_ok, addr_ok_q, pi.effective_clkpol); } |