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| author | whitequark <whitequark@whitequark.org> | 2021-03-07 03:45:41 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-07 03:45:41 -0800 |
| commit | 72ae15c77c34fe2306c3ac41c40521e9141b8cf0 (patch) | |
| tree | 3606b07a7372af728cbfa8d16dc258162f659a8b | |
| parent | b1a8e73a609d3065f1caf7a230529443b54295bc (diff) | |
| parent | c18ddbcd822410095d28c4be1c3ac3c6358622d2 (diff) | |
| download | yosys-72ae15c77c34fe2306c3ac41c40521e9141b8cf0.tar.gz yosys-72ae15c77c34fe2306c3ac41c40521e9141b8cf0.tar.bz2 yosys-72ae15c77c34fe2306c3ac41c40521e9141b8cf0.zip | |
Merge pull request #2632 from zachjs/width-limit
verilog: impose limit on maximum expression width
| -rw-r--r-- | frontends/ast/genrtlil.cc | 6 | ||||
| -rw-r--r-- | tests/verilog/absurd_width.ys | 17 | ||||
| -rw-r--r-- | tests/verilog/absurd_width_const.ys | 16 |
3 files changed, 39 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d4299bf69..e0a522430 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real if (found_real) *found_real = false; detectSignWidthWorker(width_hint, sign_hint, found_real); + + constexpr int kWidthLimit = 1 << 24; + if (width_hint >= kWidthLimit) + log_file_error(filename, location.first_line, + "Expression width %d exceeds implementation limit of %d!\n", + width_hint, kWidthLimit); } static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys new file mode 100644 index 000000000..c0d2af4c2 --- /dev/null +++ b/tests/verilog/absurd_width.ys @@ -0,0 +1,17 @@ +logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1 +read_verilog <<EOF +module top( + input inp, + output out +); + assign out = + {1024 { + {1024 { + {1024 { + inp + }} + }} + }} + ; +endmodule +EOF diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys new file mode 100644 index 000000000..b7191fd0d --- /dev/null +++ b/tests/verilog/absurd_width_const.ys @@ -0,0 +1,16 @@ +logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1 +read_verilog <<EOF +module top( + output out +); + assign out = + {1024 { + {1024 { + {1024 { + 1'b1 + }} + }} + }} + ; +endmodule +EOF |