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| author | Zachary Snow <zach@zachjs.com> | 2021-02-11 10:26:49 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-11 10:26:49 -0500 |
| commit | 73d611990d7f39b4e14ffc367c646686f0d2b209 (patch) | |
| tree | 6ed0d4b18195c987bef60a0134bf25514e4ab9ab | |
| parent | c383d156e9015cde4718f3a6bc3371dc87c3e4fe (diff) | |
| parent | 1d5f3fe5064146955dafdabafe7180ff79c95d08 (diff) | |
| download | yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.tar.gz yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.tar.bz2 yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.zip | |
Merge pull request #2578 from zachjs/genblk-port
verlog: allow shadowing module ports within generate blocks
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 11 | ||||
| -rw-r--r-- | tests/simple/genblk_port_shadow.v | 10 | ||||
| -rw-r--r-- | tests/verilog/genblk_port_decl.ys | 12 |
3 files changed, 29 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 69fd66cba..7fbd2aa27 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1784,7 +1784,13 @@ wire_name: } rewriteAsMemoryNode(node, $2); } - if (current_function_or_task == NULL) { + if (current_function_or_task) { + if (node->is_input || node->is_output) + node->port_id = current_function_or_task_port_id++; + } else if (ast_stack.back()->type == AST_GENBLOCK) { + if (node->is_input || node->is_output) + frontend_verilog_yyerror("Cannot declare module port `%s' within a generate block.", $1->c_str()); + } else { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { port_stubs[*$1] = ++port_counter; } @@ -1799,9 +1805,6 @@ wire_name: if (node->is_input || node->is_output) frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); } - } else { - if (node->is_input || node->is_output) - node->port_id = current_function_or_task_port_id++; } //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column... SET_AST_NODE_LOC(node, @1, @1); diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v new file mode 100644 index 000000000..a04631a20 --- /dev/null +++ b/tests/simple/genblk_port_shadow.v @@ -0,0 +1,10 @@ +module top(x); + generate + if (1) begin : blk + wire x; + assign x = 0; + end + endgenerate + output wire x; + assign x = blk.x; +endmodule diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys new file mode 100644 index 000000000..589d3d2e1 --- /dev/null +++ b/tests/verilog/genblk_port_decl.ys @@ -0,0 +1,12 @@ +logger -expect error "Cannot declare module port `\\x' within a generate block\." 1 +read_verilog <<EOT +module top(x); + generate + if (1) begin : blk + output wire x; + assign x = 1; + end + endgenerate + output wire x; +endmodule +EOT |