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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 16:46:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 16:46:15 -0700 |
| commit | 74ef8feeaf63b41e8948ce09d40420ccdb48957a (patch) | |
| tree | d6a11145e1d253875d37c7ec25e188afa8acd483 | |
| parent | 6bf7114bbd4075c2761a478406e02d4b23742aab (diff) | |
| download | yosys-74ef8feeaf63b41e8948ce09d40420ccdb48957a.tar.gz yosys-74ef8feeaf63b41e8948ce09d40420ccdb48957a.tar.bz2 yosys-74ef8feeaf63b41e8948ce09d40420ccdb48957a.zip | |
Fix xilinx_dsp for unsigned extensions
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 3d0b1f2c3..4e174e753 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -277,7 +277,9 @@ match postAdd index <SigBit> port(postAdd, AB)[0] === sigP[0] filter GetSize(port(postAdd, AB)) >= GetSize(sigP) filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP - filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) + // Check that remainder of AB is a sign-extension + define <bool> AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool()) + filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP)) set postAddAB AB optional endmatch |