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| author | Zachary Snow <zach@zachjs.com> | 2020-12-31 16:14:35 -0700 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2020-12-31 16:17:13 -0700 |
| commit | 75abd908294c599c9987978175b46196146c9d1d (patch) | |
| tree | d8aac5e136b6e68ef265c16ca49461527d78df19 | |
| parent | 48d0aeb09483283c46491448304bf04865e176f5 (diff) | |
| download | yosys-75abd908294c599c9987978175b46196146c9d1d.tar.gz yosys-75abd908294c599c9987978175b46196146c9d1d.tar.bz2 yosys-75abd908294c599c9987978175b46196146c9d1d.zip | |
sv: complete support for implied task/function port directions
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 10 | ||||
| -rw-r--r-- | tests/various/func_port_implied_dir.sv | 23 | ||||
| -rw-r--r-- | tests/various/func_port_implied_dir.ys | 6 |
3 files changed, 39 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 678ce6c87..6c4b06d7f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -884,7 +884,11 @@ task_func_args: task_func_port: attr wire_type range { + bool prev_was_input = true; + bool prev_was_output = false; if (albuf) { + prev_was_input = astbuf1->is_input; + prev_was_output = astbuf1->is_output; delete astbuf1; if (astbuf2 != NULL) delete astbuf2; @@ -893,6 +897,12 @@ task_func_port: albuf = $1; astbuf1 = $2; astbuf2 = checkRange(astbuf1, $3); + if (!astbuf1->is_input && !astbuf1->is_output) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + astbuf1->is_input = prev_was_input; + astbuf1->is_output = prev_was_output; + } } wire_name | { if (!astbuf1) { diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv new file mode 100644 index 000000000..0424f1b46 --- /dev/null +++ b/tests/various/func_port_implied_dir.sv @@ -0,0 +1,23 @@ +module gate(w, x, y, z); + function automatic integer bar( + integer a + ); + bar = 2 ** a; + endfunction + output integer w = bar(4); + + function automatic integer foo( + input integer a, /* implicitly input */ integer b, + output integer c, /* implicitly output */ integer d + ); + c = 42; + d = 51; + foo = a + b + 1; + endfunction + output integer x, y, z; + initial x = foo(1, 2, y, z); +endmodule + +module gold(w, x, y, z); + output integer w = 16, x = 4, y = 42, z = 51; +endmodule diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys new file mode 100644 index 000000000..b5c22a05b --- /dev/null +++ b/tests/various/func_port_implied_dir.ys @@ -0,0 +1,6 @@ +read_verilog -sv func_port_implied_dir.sv +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert |