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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-14 10:43:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-14 10:43:05 -0700 |
| commit | 75bb2c8c2472f4f09c556c09ae0ac3fb6a70d41a (patch) | |
| tree | 50fbf8c36afe0bfec844fa75b64c8c4bdf62d5f9 | |
| parent | 635b2b8939f32a3551114332147a8323217f4474 (diff) | |
| download | yosys-75bb2c8c2472f4f09c556c09ae0ac3fb6a70d41a.tar.gz yosys-75bb2c8c2472f4f09c556c09ae0ac3fb6a70d41a.tar.bz2 yosys-75bb2c8c2472f4f09c556c09ae0ac3fb6a70d41a.zip | |
design: do not delete when iterating over Design::modules() directly
| -rw-r--r-- | passes/cmds/design.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 4612760cc..8861182aa 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -340,7 +340,7 @@ struct DesignPass : public Pass { if (reset_mode || !load_name.empty() || push_mode || pop_mode) { - for (auto mod : design->modules()) + for (auto mod : design->modules().to_vector()) design->remove(mod); design->selection_stack.clear(); |