read_aiger: make $and/$not/$lut the prefix not suffix

2 files changed, 9 insertions, 9 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 8a114b18c..6a1b64a21 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -346,7 +346,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 	}
 
 	log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-	module->addNotGate(stringf("$%d$not", variable), wire_inv, wire);
+	module->addNotGate(stringf("$not$%d", variable), wire_inv, wire);
 
 	return wire;
 }
@@ -445,10 +445,10 @@ void AigerReader::parse_xaiger()
 					log_assert(o.wire == nullptr);
 					lut_mask[gray] = o.data;
 				}
-				RTLIL::Cell *output_cell = module->cell(stringf("$%d$and", rootNodeID));
+				RTLIL::Cell *output_cell = module->cell(stringf("$and$%d", rootNodeID));
 				log_assert(output_cell);
 				module->remove(output_cell);
-				module->addLut(stringf("$%d$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
+				module->addLut(stringf("$lut$%d", rootNodeID), input_sig, output_sig, std::move(lut_mask));
 			}
 		}
 		else if (c == 'r') {
@@ -620,7 +620,7 @@ void AigerReader::parse_aiger_ascii()
 		RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 		RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-		module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
+		module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
 	}
 	std::getline(f, line); // Ignore up to start of next line
 }
@@ -746,7 +746,7 @@ void AigerReader::parse_aiger_binary()
 		RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 		RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-		module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
+		module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
 	}
 }
 
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 8a6195741..1f6cdaa22 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -348,7 +348,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
 		log_assert(!design->module(ID($__abc9__)));
 		{
-			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, /*buffer.c_str()*/ "" /* map_filename */, true /* wideports */);
+			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
 			reader.parse_xaiger();
 		}
 		ifs.close();
@@ -472,16 +472,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 						// (TODO: Optimise by not cloning unless will increase depth)
 						RTLIL::IdString driver_name;
 						if (GetSize(a_bit.wire) == 1)
-							driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
+							driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
 						else
-							driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
+							driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
 						driver_lut = mapped_mod->cell(driver_name);
 					}
 
 					if (!driver_lut) {
 						// If a driver couldn't be found (could be from PI or box CI)
 						// then implement using a LUT
-						cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
+						cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
 								RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
 								RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
 								RTLIL::Const::from_string("01"));