Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

10 files changed, 170 insertions, 116 deletions

diff --git a/Makefile b/Makefile
index fd95219ee..43c4d0890 100644
--- a/Makefile
+++ b/Makefile
@@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.9+932
+YOSYS_VER := 0.9+1706
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 
@@ -128,7 +128,7 @@ bumpversion:
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 144c5be
+ABCREV = 71f2b40
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index beaed696d..212e1e561 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -386,7 +386,8 @@ struct XAigerWriter
 		if (holes_mode) {
 			struct sort_by_port_id {
 				bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
-					return a.wire->port_id < b.wire->port_id;
+					return a.wire->port_id < b.wire->port_id ||
+					    (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
 				}
 			};
 			input_bits.sort(sort_by_port_id());
@@ -526,7 +527,7 @@ struct XAigerWriter
 			RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
 			log_assert(holes_module);
 
-			dict<IdString, Cell*> cell_cache;
+			dict<IdString, std::tuple<int,int,int>> cell_cache;
 
 			int box_count = 0;
 			for (auto cell : box_list) {
@@ -535,24 +536,32 @@ struct XAigerWriter
 				RTLIL::Module* box_module = module->design->module(cell->type);
 				log_assert(box_module);
 
-				int box_inputs = 0, box_outputs = 0;
-				for (auto port_name : box_module->ports) {
-					RTLIL::Wire *w = box_module->wire(port_name);
-					log_assert(w);
-					if (w->port_input)
-						box_inputs += GetSize(w);
-					if (w->port_output)
-						box_outputs += GetSize(w);
-				}
+				auto r = cell_cache.insert(cell->type);
+				auto &v = r.first->second;
+				if (r.second) {
+					int box_inputs = 0, box_outputs = 0;
+					for (auto port_name : box_module->ports) {
+						RTLIL::Wire *w = box_module->wire(port_name);
+						log_assert(w);
+						if (w->port_input)
+							box_inputs += GetSize(w);
+						if (w->port_output)
+							box_outputs += GetSize(w);
+					}
 
-				// For flops only, create an extra 1-bit input that drives a new wire
-				//   called "<cell>.abc9_ff.Q" that is used below
-				if (box_module->get_bool_attribute("\\abc9_flop"))
-					box_inputs++;
+					// For flops only, create an extra 1-bit input that drives a new wire
+					//   called "<cell>.abc9_ff.Q" that is used below
+					if (box_module->get_bool_attribute("\\abc9_flop"))
+					    box_inputs++;
+
+					std::get<0>(v) = box_inputs;
+					std::get<1>(v) = box_outputs;
+					std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
+				}
 
-				write_h_buffer(box_inputs);
-				write_h_buffer(box_outputs);
-				write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int());
+				write_h_buffer(std::get<0>(v));
+				write_h_buffer(std::get<1>(v));
+				write_h_buffer(std::get<2>(v));
 				write_h_buffer(box_count++);
 			}
 
diff --git a/kernel/register.cc b/kernel/register.cc
index 37f2e5e1b..5d0fb3c8c 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -114,20 +114,35 @@ void Pass::run_register()
 
 void Pass::init_register()
 {
+	vector<Pass*> added_passes;
 	while (first_queued_pass) {
+		added_passes.push_back(first_queued_pass);
 		first_queued_pass->run_register();
 		first_queued_pass = first_queued_pass->next_queued_pass;
 	}
+	for (auto added_pass : added_passes)
+		added_pass->on_register();
 }
 
 void Pass::done_register()
 {
+	for (auto &it : pass_register)
+		it.second->on_shutdown();
+
 	frontend_register.clear();
 	pass_register.clear();
 	backend_register.clear();
 	log_assert(first_queued_pass == NULL);
 }
 
+void Pass::on_register()
+{
+}
+
+void Pass::on_shutdown()
+{
+}
+
 Pass::~Pass()
 {
 }
diff --git a/kernel/register.h b/kernel/register.h
index 85d552f0d..821faff3e 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -62,6 +62,9 @@ struct Pass
 	virtual void run_register();
 	static void init_register();
 	static void done_register();
+
+	virtual void on_register();
+	virtual void on_shutdown();
 };
 
 struct ScriptPass : Pass
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 5018a4888..8190d8902 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -544,6 +544,8 @@ void yosys_shutdown()
 	already_shutdown = true;
 	log_pop();
 
+	Pass::done_register();
+
 	delete yosys_design;
 	yosys_design = NULL;
 
@@ -553,7 +555,6 @@ void yosys_shutdown()
 	log_errfile = NULL;
 	log_files.clear();
 
-	Pass::done_register();
 	yosys_celltypes.clear();
 
 #ifdef YOSYS_ENABLE_TCL
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 939eff021..30b62dc79 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -182,11 +182,13 @@ struct Abc9Pass : public ScriptPass
 				run("abc9_ops -break_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
 			run("select -set abc9_holes A:abc9_holes");
 			run("flatten -wb @abc9_holes");
+run("dump @abc9_holes");
 			run("techmap @abc9_holes");
-			run("aigmap");
 			if (dff_mode || help_mode)
 				run("abc9_ops -prep_dff", "(only if -dff)");
 			run("opt -purge @abc9_holes");
+run("dump @abc9_holes");
+			run("aigmap");
 			run("wbflip @abc9_holes");
 		}
 
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 6f089447e..cc22fd474 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -144,14 +144,16 @@ void prep_dff(RTLIL::Module *module)
 
 	RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
 	if (holes_module) {
-		dict<SigSig, SigSig> replace;
+		SigMap sigmap(holes_module);
+
+		dict<SigSpec, SigSpec> replace;
 		for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
 			auto cell = it->second;
 			if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
 						"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
 				SigBit D = cell->getPort("\\D");
 				SigBit Q = cell->getPort("\\Q");
-				// Remove the DFF cell from what needs to be a combinatorial box
+				// Remove the $_DFF_* cell from what needs to be a combinatorial box
 				it = holes_module->cells_.erase(it);
 				Wire *port;
 				if (GetSize(Q.wire) == 1)
@@ -159,10 +161,10 @@ void prep_dff(RTLIL::Module *module)
 				else
 					port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
 				log_assert(port);
-				// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
-				//   in order to extract the combinatorial control logic that feeds the box
+				// Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
+				//   in order to extract just the combinatorial control logic that feeds the box
 				//   (i.e. clock enable, synchronous reset, etc.)
-				replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
+				replace.insert(std::make_pair(Q,D));
 				// Since `flatten` above would have created wires named "<cell>.Q",
 				//   extract the pre-techmap cell name
 				auto pos = Q.wire->name.str().rfind(".");
@@ -170,7 +172,7 @@ void prep_dff(RTLIL::Module *module)
 				IdString driver = Q.wire->name.substr(0, pos);
 				// And drive the signal that was previously driven by "DFF.Q" (typically
 				//   used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
-				//   wire (which itself is driven an input port) we inserted above
+				//   wire (which itself is driven an by input port) we inserted above
 				Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
 				log_assert(currQ);
 				holes_module->connect(Q, currQ);
@@ -180,7 +182,7 @@ void prep_dff(RTLIL::Module *module)
 		}
 
 		for (auto &conn : holes_module->connections_)
-			conn = replace.at(conn, conn);
+			conn.second = replace.at(sigmap(conn.second), conn.second);
 	}
 }
 
@@ -317,107 +319,105 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		log_assert(orig_box_module);
 		IdString derived_name = orig_box_module->derive(design, cell->parameters);
 		RTLIL::Module* box_module = design->module(derived_name);
-		if (box_module->has_processes())
-			Pass::call_on_module(design, box_module, "proc");
-
-		int box_inputs = 0;
-		auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
-		Cell *holes_cell = r.first->second;
-		if (r.second && box_module->get_bool_attribute("\\whitebox")) {
-			holes_cell = holes_module->addCell(cell->name, cell->type);
-			holes_cell->parameters = cell->parameters;
-			r.first->second = holes_cell;
-		}
 
-		auto r2 = box_ports.insert(cell->type);
-		if (r2.second) {
-			// Make carry in the last PI, and carry out the last PO
-			//   since ABC requires it this way
-			IdString carry_in, carry_out;
-			for (const auto &port_name : box_module->ports) {
-				auto w = box_module->wire(port_name);
-				log_assert(w);
-				if (w->get_bool_attribute("\\abc9_carry")) {
-					if (w->port_input) {
-						if (carry_in != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
-						carry_in = port_name;
-					}
-					if (w->port_output) {
-						if (carry_out != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
-						carry_out = port_name;
+		auto r = cell_cache.insert(derived_name);
+		auto &holes_cell = r.first->second;
+		if (r.second) {
+			if (box_module->has_processes())
+				Pass::call_on_module(design, box_module, "proc");
+
+			auto r2 = box_ports.insert(cell->type);
+			if (r2.second) {
+				// Make carry in the last PI, and carry out the last PO
+				//   since ABC requires it this way
+				IdString carry_in, carry_out;
+				for (const auto &port_name : box_module->ports) {
+					auto w = box_module->wire(port_name);
+					log_assert(w);
+					if (w->get_bool_attribute("\\abc9_carry")) {
+						if (w->port_input) {
+							if (carry_in != IdString())
+								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
+							carry_in = port_name;
+						}
+						if (w->port_output) {
+							if (carry_out != IdString())
+								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
+							carry_out = port_name;
+						}
 					}
+					else
+						r2.first->second.push_back(port_name);
 				}
-				else
-					r2.first->second.push_back(port_name);
-			}
 
-			if (carry_in != IdString() && carry_out == IdString())
-				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
-			if (carry_in == IdString() && carry_out != IdString())
-				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
-			if (carry_in != IdString()) {
-				r2.first->second.push_back(carry_in);
-				r2.first->second.push_back(carry_out);
+				if (carry_in != IdString() && carry_out == IdString())
+					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
+				if (carry_in == IdString() && carry_out != IdString())
+					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
+				if (carry_in != IdString()) {
+					r2.first->second.push_back(carry_in);
+					r2.first->second.push_back(carry_out);
+				}
 			}
-		}
 
-		for (const auto &port_name : box_ports.at(cell->type)) {
-			RTLIL::Wire *w = box_module->wire(port_name);
-			log_assert(w);
-			RTLIL::Wire *holes_wire;
-			RTLIL::SigSpec port_sig;
-			if (w->port_input)
-				for (int i = 0; i < GetSize(w); i++) {
+			if (box_module->get_bool_attribute("\\whitebox")) {
+				holes_cell = holes_module->addCell(cell->name, derived_name);
+
+				int box_inputs = 0;
+				for (auto port_name : box_ports.at(cell->type)) {
+					RTLIL::Wire *w = box_module->wire(port_name);
+					log_assert(w);
+					log_assert(!w->port_input || !w->port_output);
+					auto &conn = holes_cell->connections_[port_name];
+					if (w->port_input) {
+						for (int i = 0; i < GetSize(w); i++) {
+							box_inputs++;
+							RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+							if (!holes_wire) {
+								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+								holes_wire->port_input = true;
+								holes_wire->port_id = port_id++;
+								holes_module->ports.push_back(holes_wire->name);
+							}
+							conn.append(holes_wire);
+						}
+					}
+					else if (w->port_output)
+						conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+				}
+
+				// For flops only, create an extra 1-bit input that drives a new wire
+				//   called "<cell>.abc9_ff.Q" that is used below
+				if (box_module->get_bool_attribute("\\abc9_flop")) {
 					box_inputs++;
-					holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+					Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 					if (!holes_wire) {
 						holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
 						holes_wire->port_input = true;
 						holes_wire->port_id = port_id++;
 						holes_module->ports.push_back(holes_wire->name);
 					}
-					if (holes_cell)
-						port_sig.append(holes_wire);
-				}
-			if (w->port_output)
-				for (int i = 0; i < GetSize(w); i++) {
-					if (GetSize(w) == 1)
-						holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
-					else
-						holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
-					holes_wire->port_output = true;
-					holes_wire->port_id = port_id++;
-					holes_module->ports.push_back(holes_wire->name);
-					if (holes_cell)
-						port_sig.append(holes_wire);
-					else
-						holes_module->connect(holes_wire, State::S0);
+					Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
+					holes_module->connect(Q, holes_wire);
 				}
-			if (!port_sig.empty()) {
-				if (r.second)
-					holes_cell->setPort(w->name, port_sig);
-				else
-					holes_module->connect(holes_cell->getPort(w->name), port_sig);
 			}
+			else // box_module is a blackbox
+				log_assert(holes_cell == nullptr);
 		}
 
-		// For flops only, create an extra 1-bit input that drives a new wire
-		//   called "<cell>.$abc9_currQ" that is used below
-		if (box_module->get_bool_attribute("\\abc9_flop")) {
-			log_assert(holes_cell);
-
-			box_inputs++;
-			Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
-			if (!holes_wire) {
-				holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
-				holes_wire->port_input = true;
-				holes_wire->port_id = port_id++;
-				holes_module->ports.push_back(holes_wire->name);
-			}
-			Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
-			holes_module->connect(w, holes_wire);
+		for (auto port_name : box_ports.at(cell->type)) {
+			RTLIL::Wire *w = box_module->wire(port_name);
+			log_assert(w);
+			if (!w->port_output)
+				continue;
+			Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
+			holes_wire->port_output = true;
+			holes_wire->port_id = port_id++;
+			holes_module->ports.push_back(holes_wire->name);
+			if (holes_cell) // whitebox
+				holes_module->connect(holes_wire, holes_cell->getPort(port_name));
+			else // blackbox
+				holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
 		}
 	}
 }
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index d616391b2..6583f43fd 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -323,9 +323,9 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc9) {
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
+					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
 				else
-					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
+					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
 				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 51d2cbbd2..63d00027a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -556,7 +556,6 @@ struct SynthXilinxPass : public ScriptPass
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
 				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
-				abc9_opts += " -nomfs";
 				if (nowidelut)
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys
new file mode 100644
index 000000000..1142ae0b5
--- /dev/null
+++ b/tests/arch/ecp5/bug1459.ys
@@ -0,0 +1,25 @@
+read_verilog <<EOT
+module register_file(
+    input wire clk,
+    input wire write_enable,
+    input wire [63:0] write_data,
+    input wire [4:0] write_reg,
+    input wire [4:0] read1_reg,
+    output reg [63:0] read1_data,
+    );
+
+    reg [63:0] registers[0:31];
+
+    always @(posedge clk) begin
+      if (write_enable == 1'b1) begin
+        registers[write_reg] <= write_data;
+      end
+    end
+
+    always @(all) begin
+      read1_data <= registers[read1_reg];
+    end
+endmodule
+EOT
+
+synth_ecp5 -abc9