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| author | whitequark <whitequark@whitequark.org> | 2021-03-01 08:10:32 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-01 08:10:32 -0800 |
| commit | 7b47dd0f8833252715eb8297de2134804578b179 (patch) | |
| tree | bac4764aeeb252ed6e9357d056dcdf42949d8de8 | |
| parent | ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da (diff) | |
| parent | ca4b1afcb687c03837c66b657fe73363cacf1e70 (diff) | |
| download | yosys-7b47dd0f8833252715eb8297de2134804578b179.tar.gz yosys-7b47dd0f8833252715eb8297de2134804578b179.tar.bz2 yosys-7b47dd0f8833252715eb8297de2134804578b179.zip | |
Merge pull request #2617 from RobertBaruch/doc
RTLIL Documentation: switch in process is optional
| -rw-r--r-- | manual/CHAPTER_TextRtlil.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_TextRtlil.tex b/manual/CHAPTER_TextRtlil.tex index 243b56a87..5615a8707 100644 --- a/manual/CHAPTER_TextRtlil.tex +++ b/manual/CHAPTER_TextRtlil.tex @@ -241,7 +241,7 @@ See Sec.~\ref{sec:rtlil_process} for an overview of processes. <proc-stmt> ::= "process" <id> <eol> -<process-body> ::= <assign-stmt>$*$ <switch> <assign-stmt>$*$ <sync>$*$ +<process-body> ::= <assign-stmt>$*$ <switch>$?$ <assign-stmt>$*$ <sync>$*$ <assign-stmt> ::= "assign" <dest-sigspec> <src-sigspec> <eol> |