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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 12:18:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 12:18:28 -0800 |
| commit | 7cac3b1c8bab3ba7749f4e272544f3f5f3dfa1e2 (patch) | |
| tree | 15d645013f06e5ad318c99e346510f06c17fa77a | |
| parent | 8e883d92edef57214093ae7c5d8be6edb8462c8d (diff) | |
| download | yosys-7cac3b1c8bab3ba7749f4e272544f3f5f3dfa1e2.tar.gz yosys-7cac3b1c8bab3ba7749f4e272544f3f5f3dfa1e2.tar.bz2 yosys-7cac3b1c8bab3ba7749f4e272544f3f5f3dfa1e2.zip | |
abc9 -- multiple connections for inouts
| -rw-r--r-- | passes/techmap/abc9.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index de47de92e..3ec365bc0 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -898,13 +898,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri conn.first = remap_wire; conn.second = signal; in_wires++; + module->connect(conn); } if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; + module->connect(conn); } - module->connect(conn); } //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); |