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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-18 02:56:36 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-18 02:56:36 +0100 |
| commit | 839af272adeb6e15c0b1fd1c35249db4a9da9f4d (patch) | |
| tree | 4c98ec4b6d0057efab1ea42d4b91f9778714e351 | |
| parent | 091d9abc3e7a92329211d32f17ad6a49d5339fc5 (diff) | |
| download | yosys-839af272adeb6e15c0b1fd1c35249db4a9da9f4d.tar.gz yosys-839af272adeb6e15c0b1fd1c35249db4a9da9f4d.tar.bz2 yosys-839af272adeb6e15c0b1fd1c35249db4a9da9f4d.zip | |
Improved setundef random number generator
| -rw-r--r-- | passes/cmds/setundef.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 394834a36..9d59834c2 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -40,7 +40,7 @@ static RTLIL::State next_bit() next_bit_state ^= next_bit_state << 5; log_assert(next_bit_state != 0); - return ((next_bit_state >> (next_bit_state & 15)) & 1) ? RTLIL::State::S0 : RTLIL::State::S1; + return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; } struct SetundefWorker |