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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 10:26:37 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 10:26:37 -0800 |
| commit | 83d36394f86510abf944ada407d4a1f4d7eefcd0 (patch) | |
| tree | a4b45569ee7fa1a90fe38d0f9736e8f2ad2133c3 | |
| parent | d86d073ad657b5bc92b8ef020b79c070333f267f (diff) | |
| download | yosys-83d36394f86510abf944ada407d4a1f4d7eefcd0.tar.gz yosys-83d36394f86510abf944ada407d4a1f4d7eefcd0.tar.bz2 yosys-83d36394f86510abf944ada407d4a1f4d7eefcd0.zip | |
opt_merge to discard \init of '$' cells with 'Q' port when merging
| -rw-r--r-- | passes/opt/opt_merge.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index aaea6159e..643cf0215 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -323,6 +323,17 @@ struct OptMergeWorker log_signal(it.second), log_signal(other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); + + if (cell->type.begins_with("$") && it.first == ID(Q)) { + for (auto c : it.second.chunks()) { + auto jt = c.wire->attributes.find(ID(init)); + if (jt == c.wire->attributes.end()) + continue; + for (int i = c.offset; i < c.offset + c.width; i++) + jt->second[i] = State::Sx; + } + dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second))); + } } } log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); |