diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-03 07:14:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-03 07:14:20 -0700 |
| commit | 88630cd02cfb7cb124c949777280b60f66ee5eb5 (patch) | |
| tree | 81b549e89b7d25b0a9f0cb60d10ca09b490bd65b | |
| parent | f7a0434d54261834a7371727741e5cdf24ec5ca0 (diff) | |
| download | yosys-88630cd02cfb7cb124c949777280b60f66ee5eb5.tar.gz yosys-88630cd02cfb7cb124c949777280b60f66ee5eb5.tar.bz2 yosys-88630cd02cfb7cb124c949777280b60f66ee5eb5.zip | |
Disable shregmap in synth_xilinx if -retime
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b6225a1a3..df30a22de 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,8 +113,8 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff* (only without -nosrl)\n"); - log(" shregmap -tech xilinx -minlen 3 (only without -nosrl)\n"); + log(" simplemap t:$dff* (without -nosrl and without -retime only)\n"); + log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -265,7 +265,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); - if (!nosrl) { + if (!nosrl && !retime) { Pass::call(design, "simplemap t:$dff*"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } |