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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-07 10:01:11 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-07 10:04:47 +0100 |
| commit | 8a63fc51d31bca50c3d08130c3271a288af1cf4b (patch) | |
| tree | 7dad4bc48ce9cb7f58ae4efcb6c2f7370a1ee7d2 | |
| parent | dbd51d7bdafbd888186ad42e4a6f842c054f57d9 (diff) | |
| download | yosys-8a63fc51d31bca50c3d08130c3271a288af1cf4b.tar.gz yosys-8a63fc51d31bca50c3d08130c3271a288af1cf4b.tar.bz2 yosys-8a63fc51d31bca50c3d08130c3271a288af1cf4b.zip | |
Bugfix in $memrd sharing
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/opt/share.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/opt/share.cc b/passes/opt/share.cc index b80280829..c85c27427 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -710,8 +710,12 @@ struct ShareWorker RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); RTLIL::SigSpec addr1 = c1->getPort("\\ADDR"); RTLIL::SigSpec addr2 = c2->getPort("\\ADDR"); - if (addr1 != addr2) - supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act)); + if (GetSize(addr1) < GetSize(addr2)) + addr1.extend_u0(GetSize(addr2)); + else + addr2.extend_u0(GetSize(addr1)); + supercell->setPort("\\ADDR", addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); + supercell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr1)); supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA"))); supercell_aux.insert(supercell); return supercell; |