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author | Aman Goel <amangoel@umich.edu> | 2018-05-14 18:58:49 -0400 |
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committer | Aman Goel <amangoel@umich.edu> | 2018-05-14 18:58:49 -0400 |
commit | 8b9a8c7f9115e691dc832b3be3d82b55be507e99 (patch) | |
tree | 29efa1ade9363c76b0b3c64de4a2f1279cd0adf9 | |
parent | b4a303a1b7a9986881efa1040bf54c5f583d87a0 (diff) | |
download | yosys-8b9a8c7f9115e691dc832b3be3d82b55be507e99.tar.gz yosys-8b9a8c7f9115e691dc832b3be3d82b55be507e99.tar.bz2 yosys-8b9a8c7f9115e691dc832b3be3d82b55be507e99.zip |
Minor correction
Minor typo error correction in -expose with setundef
-rw-r--r-- | passes/cmds/setundef.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 0825cf83e..9b0c30cae 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -89,7 +89,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std: return wire; } - struct SetundefWorker { int next_bit_mode; @@ -304,7 +303,7 @@ struct SetundefPass : public Pass { else { string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; wire = add_wire(design, module, name, c.width, true, false, false); - module->connect(RTLIL::SigSig(c.wire, wire)); + module->connect(RTLIL::SigSig(c, wire)); } log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } |