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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-22 16:10:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-22 16:10:21 -0700 |
| commit | 8c31441ba066ea246ff1ef55c3dd6ceb4ee8d6e3 (patch) | |
| tree | 9bfeaafce64e4e16060b880aa47db7e5f20d4da0 | |
| parent | 4d71ab384d640f53435d2e4773b2277f385cda27 (diff) | |
| download | yosys-8c31441ba066ea246ff1ef55c3dd6ceb4ee8d6e3.tar.gz yosys-8c31441ba066ea246ff1ef55c3dd6ceb4ee8d6e3.tar.bz2 yosys-8c31441ba066ea246ff1ef55c3dd6ceb4ee8d6e3.zip | |
SigSpec::extract() to return as many bits as poss if out of bounds
| -rw-r--r-- | kernel/rtlil.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5d992ef2d..fd98ab4bd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3354,7 +3354,13 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector<RTLIL::SigBit>(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); + auto it = bits_.begin() + std::min<int>(offset, width_); + decltype(it) ie; + if (length >= 0) + ie = bits_.begin() + std::min<int>(offset + length, width_); + else + ie = bits_.end() + std::max<int>(length + 1, offset - width_); + return std::vector<RTLIL::SigBit>(it, ie); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) |