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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-25 19:59:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-25 19:59:33 -0700 |
| commit | 976d8030dce8cd242401933ac8ea6c8ffe8af224 (patch) | |
| tree | ccf701c493983beec0541e28e98d05640107323b | |
| parent | f14d7f0df65c6892b911c74e1674a94ad3e556db (diff) | |
| download | yosys-976d8030dce8cd242401933ac8ea6c8ffe8af224.tar.gz yosys-976d8030dce8cd242401933ac8ea6c8ffe8af224.tar.bz2 yosys-976d8030dce8cd242401933ac8ea6c8ffe8af224.zip | |
Actually use pm.st.shiftxB
| -rw-r--r-- | passes/pmgen/split_shiftx.cc | 5 | ||||
| -rw-r--r-- | passes/pmgen/split_shiftx.pmg | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc index 2af0ebecf..3cbabcd76 100644 --- a/passes/pmgen/split_shiftx.cc +++ b/passes/pmgen/split_shiftx.cc @@ -30,10 +30,11 @@ void create_split_shiftx(split_shiftx_pm &pm) if (pm.blacklist_cells.count(pm.st.shiftx)) return; SigSpec A = pm.st.shiftx->getPort("\\A"); - SigSpec B = pm.st.shiftx->getPort("\\B"); + SigSpec B = pm.st.shiftxB; + log_assert(!B.empty()); SigSpec Y = pm.st.shiftx->getPort("\\Y"); const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); - const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int(); + const int B_WIDTH = GetSize(pm.st.shiftxB); const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); int trailing_zeroes = 0; for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ; diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg index c9e0ff995..3aafe1975 100644 --- a/passes/pmgen/split_shiftx.pmg +++ b/passes/pmgen/split_shiftx.pmg @@ -12,11 +12,13 @@ match macc endmatch code shiftxB + shiftxB = port(shiftx, \B); + if (macc) { - shiftxB = port(shiftx, \B); const int b_width = param(shiftx, \B_WIDTH).as_int(); if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) shiftxB = shiftxB.extract(0, b_width-1); + if (port(macc, \Y) != shiftxB) { blacklist(shiftx); reject; |