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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-18 10:53:14 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-18 10:53:14 +0100 |
| commit | 9ee3c57e460b15acb8e1503e97fc35aa6eed0661 (patch) | |
| tree | 06999fcbfb9a7f4dbe59b54c03c25e6629a6b0bb | |
| parent | cdb566b2d6a998ccaf5406f584e3ec810973dff9 (diff) | |
| parent | 38e72d6e13b908007577b7782078ac8b968496f5 (diff) | |
| download | yosys-9ee3c57e460b15acb8e1503e97fc35aa6eed0661.tar.gz yosys-9ee3c57e460b15acb8e1503e97fc35aa6eed0661.tar.bz2 yosys-9ee3c57e460b15acb8e1503e97fc35aa6eed0661.zip | |
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
Fix #1496.
| -rw-r--r-- | passes/techmap/extract_fa.cc | 12 | ||||
| -rw-r--r-- | tests/various/bug1496.ys | 13 |
2 files changed, 21 insertions, 4 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 29700c37b..9f3bb525b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -262,10 +262,14 @@ struct ExtractFaWorker pool<SigBit> new_leaves = leaves; new_leaves.erase(bit); - if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A)))); - if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B)))); - if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C))))); - if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D))))); + for (auto port : {ID::A, ID::B, ID(C), ID(D)}) { + if (!cell->hasPort(port)) + continue; + auto bit = sigmap(SigBit(cell->getPort(port))); + if (!bit.wire) + continue; + new_leaves.insert(bit); + } if (GetSize(new_leaves) > maxbreadth) continue; diff --git a/tests/various/bug1496.ys b/tests/various/bug1496.ys new file mode 100644 index 000000000..d050161dc --- /dev/null +++ b/tests/various/bug1496.ys @@ -0,0 +1,13 @@ +read_ilang << EOF +module \top + wire input 1 \A + wire output 2 \Y + cell $_AND_ \sub + connect \A \A + connect \B 1'0 + connect \Y \Y + end +end +EOF + +extract_fa |