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| author | whitequark <whitequark@whitequark.org> | 2018-12-16 18:25:53 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-16 18:26:00 +0000 |
| commit | 9f5c7017ff89ad914b6b9be0620996d77e24f71b (patch) | |
| tree | a1ef85ecaadc1a7cce03bfbec30e4dac036800d9 | |
| parent | ddff75b60ab6b29bbc8425c7f5ac2e6ebbbf32a6 (diff) | |
| download | yosys-9f5c7017ff89ad914b6b9be0620996d77e24f71b.tar.gz yosys-9f5c7017ff89ad914b6b9be0620996d77e24f71b.tar.bz2 yosys-9f5c7017ff89ad914b6b9be0620996d77e24f71b.zip | |
Update CHANGELOG.
| -rw-r--r-- | CHANGELOG | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -9,6 +9,13 @@ Yosys 0.8 .. Yosys 0.8-dev * Various - Added $changed support to read_verilog - Added "write_edif -attrprop" + - Added "ice40_unlut" pass + - Added "opt_lut" pass + - Added "synth_ice40 -relut" + - Added "synth_ice40 -noabc" + - Added "gate2lut.v" techmap rule + - Added "rename -src" + - Added "equiv_opt" pass Yosys 0.7 .. Yosys 0.8 |