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| author | whitequark <whitequark@whitequark.org> | 2021-07-20 13:12:11 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-20 13:12:11 +0000 |
| commit | a04844bdf805b719ec8c185e065a6bc4f7c3e2d5 (patch) | |
| tree | d6e18d1791456305625069d9a07c71e66421525b | |
| parent | 72beee2ccc0454816cddf69cde9b71a99b033e12 (diff) | |
| parent | 1a6ddf78921290851ca7bbe7605d9e146055dc39 (diff) | |
| download | yosys-a04844bdf805b719ec8c185e065a6bc4f7c3e2d5.tar.gz yosys-a04844bdf805b719ec8c185e065a6bc4f7c3e2d5.tar.bz2 yosys-a04844bdf805b719ec8c185e065a6bc4f7c3e2d5.zip | |
Merge pull request #2885 from whitequark/cxxrtl-fix-2883
cxxrtl: treat wires with multiple defs as not inlinable
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 24422712b..95ad6a86e 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -326,8 +326,14 @@ struct FlowGraph { for (auto bit : sig.bits()) bit_has_state[bit] |= is_ff; // Only comb defs of an entire wire in the right order can be inlined. - if (!is_ff && sig.is_wire()) - wire_def_inlinable[sig.as_wire()] = inlinable; + if (!is_ff && sig.is_wire()) { + // Only a single def of a wire can be inlined. (Multiple defs of a wire are unsound, but we + // handle them anyway to avoid assertion failures later.) + if (!wire_def_inlinable.count(sig.as_wire())) + wire_def_inlinable[sig.as_wire()] = inlinable; + else + wire_def_inlinable[sig.as_wire()] = false; + } } void add_uses(Node *node, const RTLIL::SigSpec &sig) |