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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 16:02:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 16:02:40 -0700 |
| commit | a41553a86125d58a0811975aa8636388615ba239 (patch) | |
| tree | 182f9ed3667ab6c1381913cf85f161470a06347f | |
| parent | 4a6b9af227cb22e89fd463c665016544060d2acd (diff) | |
| download | yosys-a41553a86125d58a0811975aa8636388615ba239.tar.gz yosys-a41553a86125d58a0811975aa8636388615ba239.tar.bz2 yosys-a41553a86125d58a0811975aa8636388615ba239.zip | |
read_xaiger() to name box signals
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7adfacb53..399e46737 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -689,23 +689,27 @@ void AigerReader::post_process() RTLIL::Wire* w = box_module->wire(port_name); log_assert(w); RTLIL::SigSpec rhs; + RTLIL::Wire* wire = nullptr; for (int i = 0; i < GetSize(w); i++) { if (w->port_input) { log_assert(static_cast<unsigned>(co_count) < outputs.size()); - RTLIL::Wire* wire = outputs[co_count++]; + wire = outputs[co_count++]; log_assert(wire); log_assert(wire->port_output); wire->port_output = false; - rhs.append(wire); } if (w->port_output) { log_assert(static_cast<unsigned>(pi_count + ci_count) < inputs.size()); - RTLIL::Wire* wire = inputs[pi_count + ci_count++]; + wire = inputs[pi_count + ci_count++]; log_assert(wire); log_assert(wire->port_input); wire->port_input = false; - rhs.append(wire); } + rhs.append(wire); + if (GetSize(w) == 1) + module->rename(wire, RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)))); + else + module->rename(wire, RTLIL::escape_id(stringf("%s.%s[%d]", log_id(cell), log_id(port_name), i))); } cell->setPort(port_name, rhs); } |