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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 17:45:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 17:45:02 -0700 |
| commit | aaeaab4ac035aaf79f46873e27b8d464675d1c9c (patch) | |
| tree | 8c1d0eced3f3153daf125acd2a80eee5adcc60ae | |
| parent | 6bb8e6a7267b4e3d8c1717cde87d41d04fdac82d (diff) | |
| download | yosys-aaeaab4ac035aaf79f46873e27b8d464675d1c9c.tar.gz yosys-aaeaab4ac035aaf79f46873e27b8d464675d1c9c.tar.bz2 yosys-aaeaab4ac035aaf79f46873e27b8d464675d1c9c.zip | |
Rename to techmap_guard
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index be69ae256..f52397c9f 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -205,6 +205,7 @@ module DSP48E1 ( parameter [6:0] IS_OPMODE_INVERTED = 7'b0; parameter _TECHMAP_CELLTYPE_ = ""; + localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); generate if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin @@ -232,9 +233,9 @@ module DSP48E1 ( \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; - else if (_TECHMAP_CELLTYPE_ != "") + else if (techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - if (ADREG == 1 && _TECHMAP_CELLTYPE_ != "") + if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); if (PREG == 0) begin if (MREG == 1) |