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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 16:17:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 16:17:12 -0700 |
| commit | ada130b4599db74744df34d8608611fd746bf08a (patch) | |
| tree | 0c40b6d61cee12fbc4f450311c46d4692d842198 | |
| parent | c7483917307bd1c281b159fe15f0f79af4e305b3 (diff) | |
| download | yosys-ada130b4599db74744df34d8608611fd746bf08a.tar.gz yosys-ada130b4599db74744df34d8608611fd746bf08a.tar.bz2 yosys-ada130b4599db74744df34d8608611fd746bf08a.zip | |
Also cope with duplicated CIs
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 0b0f6dd2e..0d81cc2fd 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -446,12 +446,30 @@ next_line: log_assert(wire); log_assert(wire->port_input); - if (index == 0) - module->rename(wire, escaped_symbol); + if (index == 0) { + // Cope with the fact that a CI might be identical + // to a PI (necessary due to ABC); in those cases + // simply connect the latter to the former + RTLIL::Wire* existing = module->wire(escaped_symbol); + if (!existing) + module->rename(wire, escaped_symbol); + else { + wire->port_input = false; + module->connect(wire, existing); + } + } else if (index > 0) { - module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index); + RTLIL::Wire* existing = module->wire(indexed_name); + if (!existing) { + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + } + else { + module->connect(wire, existing); + wire->port_input = false; + } } } else if (type == "output") { |