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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-26 13:42:41 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-26 13:42:41 -0700 |
| commit | af15b92c861f11d1f4b5016fed0cb8cb45af9175 (patch) | |
| tree | aa7ad2b18b68fd5bf492daf8f32a6495d9b05914 | |
| parent | a922d705d4c5e5c2f0cfc59f31fa11901ef307e1 (diff) | |
| download | yosys-af15b92c861f11d1f4b5016fed0cb8cb45af9175.tar.gz yosys-af15b92c861f11d1f4b5016fed0cb8cb45af9175.tar.bz2 yosys-af15b92c861f11d1f4b5016fed0cb8cb45af9175.zip | |
Renamed GP4_V* cells to GP_V* for consistency
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 4602c6cc4..54e5a423c 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -55,10 +55,11 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT); assign OUT = INIT[{IN3, IN2, IN1, IN0}]; endmodule -module GP4_VDD(output OUT); +module GP_VDD(output OUT); assign OUT = 1; endmodule -module GP4_VSS(output OUT); +module GP_VSS(output OUT); assign OUT = 0; endmodule + |