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| author | whitequark <whitequark@whitequark.org> | 2021-01-04 14:04:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-04 14:04:17 +0000 |
| commit | b00e55a16a53cebf85b0e4f381e4d92aaaeda0aa (patch) | |
| tree | 5e516dba6292eb874182f6980ea77271631fe58a | |
| parent | b72c29465392c8d260ddf55def169438f7fb64b2 (diff) | |
| parent | 87637e835922884fed301fb3580bb049c2b4d7bb (diff) | |
| download | yosys-b00e55a16a53cebf85b0e4f381e4d92aaaeda0aa.tar.gz yosys-b00e55a16a53cebf85b0e4f381e4d92aaaeda0aa.tar.bz2 yosys-b00e55a16a53cebf85b0e4f381e4d92aaaeda0aa.zip | |
Merge pull request #2522 from tomverbeure/simlib_typos2
Fix some trivial typos.
| -rw-r--r-- | techlibs/common/simlib.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index e94884025..5c9efad27 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -237,7 +237,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_and (A, B, Y) +//- $reduce_and (A, Y) //- //- An AND reduction. This corresponds to the Verilog unary prefix '&' operator. //- @@ -264,7 +264,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_or (A, B, Y) +//- $reduce_or (A, Y) //- //- An OR reduction. This corresponds to the Verilog unary prefix '|' operator. //- @@ -291,7 +291,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_xor (A, B, Y) +//- $reduce_xor (A, Y) //- //- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator. //- @@ -318,7 +318,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_xnor (A, B, Y) +//- $reduce_xnor (A, Y) //- //- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator. //- @@ -345,7 +345,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_bool (A, B, Y) +//- $reduce_bool (A, Y) //- //- An OR reduction. This cell type is used instead of $reduce_or when a signal is //- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'. |