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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:31:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:31:47 +0200 |
| commit | b03aec6e3212a387e3d255583476d472d16663f1 (patch) | |
| tree | bb944d90d8d6f619a950760747b8340249e2df58 | |
| parent | 027819c7e8ba3b1f9c7eb4864fa221a4f3b01092 (diff) | |
| download | yosys-b03aec6e3212a387e3d255583476d472d16663f1.tar.gz yosys-b03aec6e3212a387e3d255583476d472d16663f1.tar.bz2 yosys-b03aec6e3212a387e3d255583476d472d16663f1.zip | |
Added RTLIL::Module::connect(const RTLIL::SigSig&)
| -rw-r--r-- | kernel/rtlil.cc | 5 | ||||
| -rw-r--r-- | kernel/rtlil.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2378e95c5..ce4ecea6f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -873,6 +873,11 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) return a->port_id < b->port_id; } +void RTLIL::Module::connect(const RTLIL::SigSig &conn) +{ + connections_.push_back(conn); +} + void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs) { connections_.push_back(RTLIL::SigSig(lhs, rhs)); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a2320873a..4f91b720d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -288,6 +288,7 @@ struct RTLIL::Module virtual void check(); virtual void optimize(); + void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); void fixup_ports(); |