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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-18 09:50:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-18 09:50:37 -0700 |
| commit | b304744d1506ae5a672639b6baab43c9bce97f00 (patch) | |
| tree | a7e7dcf5296e938e8520eaae7956b0e759d39c88 | |
| parent | da3d2eedd2b6391621e81b3eaaa28a571e058f9d (diff) | |
| download | yosys-b304744d1506ae5a672639b6baab43c9bce97f00.tar.gz yosys-b304744d1506ae5a672639b6baab43c9bce97f00.tar.bz2 yosys-b304744d1506ae5a672639b6baab43c9bce97f00.zip | |
Clean up
| -rw-r--r-- | techlibs/ecp5/cells_map.v | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 53a89e8a3..b504d51e2 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -70,6 +70,8 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; // Need to swap input ordering, and fix init accordingly, // to match ABC's expectation of LUT inputs in non-decreasing @@ -86,19 +88,15 @@ module \$lut (A, Y); endfunction function [2**P_WIDTH-1:0] permute_init; - input [2**P_WIDTH-1:0] orig; integer i; begin permute_init = 0; for (i = 0; i < 2**P_WIDTH; i = i + 1) - permute_init[i] = orig[permute_index(i)]; + permute_init[i] = LUT[permute_index(i)]; end endfunction - parameter [2**P_WIDTH-1:0] P_LUT = permute_init(LUT); - - input [WIDTH-1:0] A; - output Y; + parameter [2**P_WIDTH-1:0] P_LUT = permute_init(); generate if (WIDTH == 1) begin |