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| author | whitequark <whitequark@whitequark.org> | 2020-06-19 01:13:19 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-19 01:13:19 +0000 |
| commit | b3b9f1bf2effdecbb8a1a334aa637fccedb211e8 (patch) | |
| tree | 8e72b9e23d26800fc2f84db579eb2e91df267d58 | |
| parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
| parent | 76dfa817904c5fa564234e020fe0898343a8523f (diff) | |
| download | yosys-b3b9f1bf2effdecbb8a1a334aa637fccedb211e8.tar.gz yosys-b3b9f1bf2effdecbb8a1a334aa637fccedb211e8.tar.bz2 yosys-b3b9f1bf2effdecbb8a1a334aa637fccedb211e8.zip | |
Merge pull request #2170 from boqwxp/cutpoint-efficiency
cutpoint: Improve efficiency by iterating over module ports instead of module wires
| -rw-r--r-- | passes/sat/cutpoint.cc | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 26cc69211..27dc10523 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -126,15 +126,16 @@ struct CutpointPass : public Pass { } vector<Wire*> rewrite_wires; - for (auto wire : module->wires()) { - if (!wire->port_input) - continue; - int bit_count = 0; - for (auto &bit : sigmap(wire)) - if (cutpoint_bits.count(bit)) - bit_count++; - if (bit_count) - rewrite_wires.push_back(wire); + for (auto id : module->ports) { + RTLIL::Wire *wire = module->wire(id); + if (wire->port_input) { + int bit_count = 0; + for (auto &bit : sigmap(wire)) + if (cutpoint_bits.count(bit)) + bit_count++; + if (bit_count) + rewrite_wires.push_back(wire); + } } for (auto wire : rewrite_wires) { |