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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 21:43:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 21:43:50 -0700 |
| commit | b47bb5c8100bf24c7075dc322f201779eda280b7 (patch) | |
| tree | 2e4810b598760f511a4c6eed22f87f8478e8f251 | |
| parent | 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 (diff) | |
| download | yosys-b47bb5c8100bf24c7075dc322f201779eda280b7.tar.gz yosys-b47bb5c8100bf24c7075dc322f201779eda280b7.tar.bz2 yosys-b47bb5c8100bf24c7075dc322f201779eda280b7.zip | |
Fix typo in check_label()
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1cddd2a92..41429b338 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -339,7 +339,7 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); } - if (check_label("map_dsp"), "(skip if '-nodsp')") { + if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " |