Add error for cell output ports that are connected to constants

1 files changed, 21 insertions, 20 deletions

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 41c1cfded..c460fbbfc 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -620,34 +620,31 @@ struct HierarchyPass : public Pass {
 			}
 		}
 
-		if (!keep_portwidths)
+		for (auto module : design->modules())
+		for (auto cell : module->cells())
 		{
-			for (auto module : design->modules())
-			for (auto cell : module->cells())
-			{
-				if (GetSize(cell->parameters) != 0)
-					continue;
-
-				Module *m = design->module(cell->type);
+			if (GetSize(cell->parameters) != 0)
+				continue;
 
-				if (m == nullptr || m->get_bool_attribute("\\blackbox"))
-					continue;
+			Module *m = design->module(cell->type);
 
-				for (auto &conn : cell->connections())
-				{
-					Wire *w = m->wire(conn.first);
+			if (m == nullptr || m->get_bool_attribute("\\blackbox"))
+				continue;
 
-					if (w == nullptr || w->port_id == 0)
-						continue;
+			for (auto &conn : cell->connections())
+			{
+				Wire *w = m->wire(conn.first);
 
-					if (GetSize(conn.second) == 0)
-						continue;
+				if (w == nullptr || w->port_id == 0)
+					continue;
 
-					if (GetSize(w) == GetSize(conn.second))
-						continue;
+				if (GetSize(conn.second) == 0)
+					continue;
 
-					SigSpec sig = conn.second;
+				SigSpec sig = conn.second;
 
+				if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
+				{
 					if (GetSize(w) < GetSize(conn.second))
 					{
 						int n = GetSize(conn.second) - GetSize(w);
@@ -669,6 +666,10 @@ struct HierarchyPass : public Pass {
 								log_id(conn.first), GetSize(conn.second), GetSize(sig));
 					cell->setPort(conn.first, sig);
 				}
+
+				if (w->port_output && !w->port_input && sig.has_const())
+					log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
+							log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
 			}
 		}