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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 13:58:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 13:58:10 -0700 |
| commit | b824a56cde5aa692da2dc6b6a0d161a98daac6ef (patch) | |
| tree | e2f2df815b06e44ebbf40ec5fe5cd5e2867c76f7 | |
| parent | 15dfbc812517a284848618eb60e3f9875c2e26ce (diff) | |
| download | yosys-b824a56cde5aa692da2dc6b6a0d161a98daac6ef.tar.gz yosys-b824a56cde5aa692da2dc6b6a0d161a98daac6ef.tar.bz2 yosys-b824a56cde5aa692da2dc6b6a0d161a98daac6ef.zip | |
Comment to explain separating CREG packing
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 86472feb5..a145ab184 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -606,6 +606,14 @@ struct XilinxDspPass : public Pass { xilinx_dsp_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_pack(xilinx_dsp_pack); } + // Separating out CREG packing is necessary since there + // is no guarantee that the cell ordering corresponds + // to the "expected" case (i.e. the order in which + // they appear in the source) thus the possiblity + // existed that a register got packed as CREG into a + // downstream DSP that should have otherwise been a + // PREG of an upstream DSP that had not been pattern + // matched yet { xilinx_dsp_CREG_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_packC(xilinx_dsp_packC); |