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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:06:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:06:02 -0800 |
| commit | b951ca9e1c25b0c9c021419c3e537c743dca6216 (patch) | |
| tree | cb2f1090345862d1b64207085fdb85faed526996 | |
| parent | ec95fbb273872ed41e2baadb644a311d31c3ee79 (diff) | |
| download | yosys-b951ca9e1c25b0c9c021419c3e537c743dca6216.tar.gz yosys-b951ca9e1c25b0c9c021419c3e537c743dca6216.tar.bz2 yosys-b951ca9e1c25b0c9c021419c3e537c743dca6216.zip | |
abc9_ops: fix -reintegrate handling of $__ABC9_DELAY
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index af4073594..816c0276a 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -659,7 +659,7 @@ void reintegrate(RTLIL::Module *module) bit_drivers[i].insert(mapped_cell->name); } } - else if (mapped_cell->type == ID($__ABC9_DELAY)) { + else if (box_lookup.at(mapped_cell->type, IdString()) == ID($__ABC9_DELAY)) { SigBit I = mapped_cell->getPort(ID(i)); SigBit O = mapped_cell->getPort(ID(o)); if (I.wire) @@ -671,7 +671,8 @@ void reintegrate(RTLIL::Module *module) } else { RTLIL::Cell *existing_cell = module->cell(mapped_cell->name); - log_assert(existing_cell); + if (!existing_cell) + log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell)); log_assert(mapped_cell->type.begins_with("$__boxid")); auto type = box_lookup.at(mapped_cell->type, IdString()); |