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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:42:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:42:02 -0700 |
| commit | bfb8b3018bbe2017ab35fbdc21813f69c56514bb (patch) | |
| tree | 9854dec4133cf5139782c4a02457e5e3330433d0 | |
| parent | 09841c2ac1f36d06faada27093a2cf0cdfb6cb42 (diff) | |
| download | yosys-bfb8b3018bbe2017ab35fbdc21813f69c56514bb.tar.gz yosys-bfb8b3018bbe2017ab35fbdc21813f69c56514bb.tar.bz2 yosys-bfb8b3018bbe2017ab35fbdc21813f69c56514bb.zip | |
Fix spacing
| -rw-r--r-- | tests/various/specify.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index aea0d0fc5..68d3e33fc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -14,15 +14,15 @@ module test ( endmodule module test2 ( - input A, B, + input A, B, output Q ); - xor (Q, A, B); + xor (Q, A, B); specify //specparam T_rise = 1; - //specparam T_fall = 2; - `define T_rise 1 - `define T_fall 2 - (A => Q) = (`T_rise,`T_fall); + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); endspecify endmodule |