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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 15:13:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 15:13:18 -0700 |
| commit | c39b1a6fcf648203df10d640c72e073f455ddc32 (patch) | |
| tree | 82a6d9d6e1a5c258f4ac1198ae968ffcf5b5c5d2 | |
| parent | ed7540a46f22151d6c87205df92bc52f5e875130 (diff) | |
| download | yosys-c39b1a6fcf648203df10d640c72e073f455ddc32.tar.gz yosys-c39b1a6fcf648203df10d640c72e073f455ddc32.tar.bz2 yosys-c39b1a6fcf648203df10d640c72e073f455ddc32.zip | |
Add comment about supporting $dffe in ice40_dsp
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 040332539..b6da1d2f6 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -12,6 +12,7 @@ match mul endmatch match ffA + // TODO: Support $dffe too by checking if all enable signals are identical select ffA->type.in($dff) filter !port(mul, \A).remove_const().empty() filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set()) |