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| author | whitequark <whitequark@whitequark.org> | 2021-04-09 09:46:53 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-04-09 09:46:53 +0000 |
| commit | c5c57e3f5e169aa13bf4f8ce064d7dc3a53616d7 (patch) | |
| tree | a7cd4ea3a30f39f8656bb5186e421e07b77da3f0 | |
| parent | 0ccc7229c02449618209a20d66b9fa07e3ea79f2 (diff) | |
| download | yosys-c5c57e3f5e169aa13bf4f8ce064d7dc3a53616d7.tar.gz yosys-c5c57e3f5e169aa13bf4f8ce064d7dc3a53616d7.tar.bz2 yosys-c5c57e3f5e169aa13bf4f8ce064d7dc3a53616d7.zip | |
flatten: rewrite memid in memwr actions.
| -rw-r--r-- | passes/techmap/flatten.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index f35b7ff60..0509eedb8 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -122,6 +122,9 @@ struct FlattenWorker for (auto &tpl_proc_it : tpl->processes) { RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second); map_attributes(cell, new_proc, tpl_proc_it.second->name); + for (auto new_proc_sync : new_proc->syncs) + for (auto &memwr_action : new_proc_sync->mem_write_actions) + memwr_action.memid = memory_map.at(memwr_action.memid).str(); auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); }; new_proc->rewrite_sigspecs(rewriter); design->select(module, new_proc); |