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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 01:53:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 01:53:22 +0200 |
| commit | c7afbd9d8efcf3045d9e4244600ce8d8e0d40b6d (patch) | |
| tree | 95b26c00b7786bf8ea5090826a2551ba6fc8c79b | |
| parent | 978a933b6af8863200096bd3a56780e3378e4848 (diff) | |
| download | yosys-c7afbd9d8efcf3045d9e4244600ce8d8e0d40b6d.tar.gz yosys-c7afbd9d8efcf3045d9e4244600ce8d8e0d40b6d.tar.bz2 yosys-c7afbd9d8efcf3045d9e4244600ce8d8e0d40b6d.zip | |
Fixed bug in "read_verilog -ignore_redef"
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 551859ebf..ec9616be3 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -947,7 +947,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (!ignore_redef) log_error("Re-definition of module `%s' at %s:%d!\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - log_error("Ignoring re-definition of module `%s' at %s:%d!\n", + log("Ignoring re-definition of module `%s' at %s:%d!\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); continue; } |